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DVB-S demodulator / DSNG demodulator
Product code: CMS0048
The CMS0048 has been designed from the ground-up for high-speed and gate-efficient implementation on FPGA and ASIC platforms and offers very high performance when combined with either the integrated FEC decoder or an external advanced FEC decoder.
The demodulator provides an adaptable starting point for receiver sub-systems to be used in both the current and next-generation of digital TV set-top-boxes, VSAT terminals and related test and monitoring equipment.
Block diagram
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Safari Plug-in
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Standards compliance
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ETSI EN 301 210
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ETSI EN 300 421
Features
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Optional integrated FEC decoding.
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Wide carrier acquisition range.
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Automatic QAM mode, FEC and spectral inversion searching.
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Programmable symbol rate recovery
few kSymb/s to >45 MSymb/s.
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Real IF, zero-IF or near-zero-IF.
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Variable ADC sampling frequency.
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QPSK, 8PSK, 16-QAM.
Applications
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ASICs for digital satellite TV reception.
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High-end interactive satellite terminals.
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Test, measurement and broadcast monitoring equipment.
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Multi-standard, adaptable (software defined) receivers.
Implementation
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Single external clock source.
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Single external analogue AGC loop.
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All-digital timing and carrier recovery.
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Digital channel filtering.
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Optimised for ASIC, Xilinx and Altera.
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Evaluation boards available.
Plug-ins / Extensions
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Group-delay equalisation.
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Block diagram
Release note
Technical data brief, 
Altera Megacore,